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NEW SYSTEMVERILOG AND UVM FLEXIBLE TRAINING

In association with the Doulos Certified Training Partner in India - Test & Verification Solutions - we are pleased to announce a unique flexible training program available in Bangalore:

Courses available: SystemVerilog Flexible Training and UVM Flexible Training

Course features:

These flexible courses are self-paced training programs based on Doulos online training materials which are accessible on-demand for the duration of the training.
Location: Online on-demand during week days. T&VS Bangalore office (for Saturday lab sessions)
Duration:
- Fast Track Course: 4 weeks (approx 4 hours per day, 5 days per week)
- Slow Track Course: 8 weeks (approx 2 hours per day, 5 days per week)

Delegates also have access to :
- Expert tutor support (by email) to answer queries and provide support for the labs.
- Saturday workshops at the end of each week for both the Fast Track and Slow Track located the T&VS Bangalore Offices including:
  - 6 hours of assisted Face-to-Face labs - for the Doulos practical online labs
  - 2 hours of lab sessions with T&VS VIP and test benches.
- online access to EDA playground - an online portal for running labs and having group discussions.
Delegates will receive a "Certificate of Completion" at the end of the training

Interested? Email your contact details to Doulos today and we will call you back »

View full international training schedule »

Best-in-Class Training

For over 25 years, Doulos has set the global standard for high quality, independent technical training in hardware design and verification, embedded software and system design.

Offered in cooperation with verification specialists Test and Verification Solutions India Pvt Ltd, the courses on offer deliver project ready skills and expert knowhow in SystemVerilog/UVM, VHDL, the latest Arm Cores, and system level modelling using SystemC and TLM-2.0.

Upcoming Live Webinars

A Guide to Productivity in Vivado using SystemVerilog

Wednesday February 18 2026

1 hour session (All Time Zones)

This webinar explores the features of SystemVerilog that are useful for RTL synthesis using the Vivado™ Design Suite from AMD, showing how the RTL SystemVerilog language constructs have been optimized for productivity and reliability.

cocotb - An Introduction for Python Programmers

Friday February 20 2026

1 hour session (All Time Zones)

With many engineers having a working knowledge of Python, cocotb can prove a highly effective verification tool. This webinar will help you get started!

What is an SBOM and why should I care?

Wednesday February 25 2026

1 hour session (All Time Zones)

In this webinar we are going to explain in as few words as possible what a Software Bill Of Materials (SBOM) is and why we need to know about them in embedded systems development.

Anatomy of an Embedded Linux System

Friday March 06 2026

1 hour session (All Time Zones)

This introductory webinar will examine each of the components required for Linux to work on an embedded system. It will review how these components fit into the system and what functionality they provide for development and in the final deployed product.