Thanks for taking the time to visit Doulos at this year's conference
This page has brought together a range of Doulos courses and FREE webinars and tutorials for you. Enjoy!
If you would like to explore training options with Doulos, check out the listing below and then contact your local Doulos team directly, or complete a webform*.
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Upcoming KnowHow Webinars
The VHDL language models hardware as a network of processes. Each process is a little bit of software that models a little bit of hardware. These processes communicate using signals. Having a good understanding of the mechanisms involved is vital to being able to write and understand VHDL code.
In this 45 minute webinar, Doulos Senior Member Technical Staff, Matthew Taylor, will explain these mechanisms through examples which are executed live on EDA Playground.
Topics covered are:
- Processes, Signal Assignments and Drivers
- Issues with multiple drivers, Longest Static Prefix
- Resolution Functions
- Implementing UVM-like Objections
- Driving Signals from Procedures
- Signal Attributes
- Passive Processes
- Force and Release
All attendees will receive access to the examples on EDA Playground using the Riviera-PRO™ Advanced Verification Platform from our webinar partner Aldec.
EDA Playground is an online simulation and synthesis environment provided by Doulos that is free to register and use. Find out more and start here: www.edaplayground.com
REGISTER NOW FOR THIS FREE KNOWHOW WEBINAR »
Doulos Co-Founder & Technical Fellow John Aynsley will teach the core principles necessary to understand and use SystemVerilog Assertions, focusing on the aspects of SVA that are applicable to both formal verification and simulation.
Particular emphasis will be placed on the core semantics of temporal logic so that you will be able to write your own assertions, understand what you are doing, and avoid the many pitfalls that trap beginners.
SVA is really not hard if you approach it properly!
Attendees will also receive access to a set of related examples on EDA Playground. EDA Playground is an online simulation and synthesis environment provided by Doulos that is free to register and use. Find out more and start here: www.edaplayground.com
It is partnered with Synopsys and examples will be shared using VCS on EDA Playground. VC Formal.
Attendance is FREE and live Q&A will be provided throughout the broadcast.
REGISTER NOW FOR THIS FREE KNOWHOW WEBINAR »
This webinar will examine how AI can be used to help do a better job of engineering. It will cover the most applicable subsets of AI for hardware design and verification and how they can be applied.
Design & Verification Expert, Doug Smith will:
- Look at the basics of AI to help identify the right terminology and subsets needed for design and verification
- Consider the practical application of Large Language Models (LLMs) in the EDA domain including the use of:
- Chaining
- Workflows and agents
- Document stores
- Prompting
- Connecting
- Model Context Protocol
- Explore how these can be put to work in engineering projects
- Provide an overview of how Siemens EDA are providing new AI-powered verification solutions in Questa One
REGISTER NOW FOR THIS FREE KNOWHOW WEBINAR »
Check out the latest live webinar schedule »
KnowHow Webinars On-Demand and Tutorials
cocotb is a Python-based framework, created to enable the rapid construction of verification environments for digital designs. With many engineers having a working knowledge of Python, cocotb can prove a highly effective verification tool.
This webinar will help you get started by covering:
- The principles of cocotb co-simulation and how cocotb fits into the design and verification flow
- Communication between the Python world and VHDL/SystemVerilog designs - Handling concurrency in cocotb
- Sychronization and timing for verifying RTL designs
- Structuring a cocotb test bench
- Running cocotb tests
- An example cocotb-driven simulation
This webinar is run in partnership with Aldec and will feature examples running in Riviera-PRO™ using the free online simulation environment from Doulos EDA Playground. Both VHDL and SystemVerilog designs under test will be shown.
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(ONLY AVAILABLE UNTIL WEDNESDAY MARCH 11, 2026)
This webinar will explore the most common mistakes users of SystemVerilog make. These mistakes have been identified by observing the lab work of students participating in Doulos training classes. The webinar aims to help you avoid the pitfalls and, in the process, get your designs working faster.
Doulos CTI Brian Jensen, will explore the topics listed below and provide useful tips and resources to help you. Practical examples will be provided using QuestaSim from Siemens-EDA in the online simulation environment EDA Playground. The webinar will include live interactive Q&A participation for attendees with Doulos technical experts.
Topics include:
- Wire vs Variable Assignments
- Static vs Automatic Variables
- Static vs Automatic Tasks
- Assignments in Tasks – Pass-by-Copy
- Assignments in Tasks – Pass-by
- Reference
- Enumerations
- struct and packed struct
- Equality Operators
- Equality between vectors
- SVA Temporal Behavior
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In this paper, eight common asynchronous scenarios are presented and SVA solutions for checking them. In addition, an alternative approach using a global fast clock is presented as both a portable simulation solution and something that works for both formal verification and emulation. Lastly, incorporating functional coverage into the asynchronous checking is also discussed.
VIEW THIS PAPER ON THE DOULOS WEBSITE NOW »
Formal verification is known to work well in areas like control logic, interface protocols, and so on, but it is often dismissed for use on data paths since capacity becomes a significant issue. In particular, packet based protocols have potentially very large state spaces, which can pose a problem for formal. However, in this paper, a step by step process is presented, showing how to decompose a frame of data into simple formal constraints, modeling code, and assertions, which allows formal to fully explore the entire packet state space.
VIEW THIS TUTORIAL ON THE DOULOS WEBSITE NOW »
An advantage of using formal verification is how quickly a formal environment can be created with a few simple properties that immediately start finding design issues. However, not all design behaviors are easily modeled using SystemVerilog's property syntax, resulting in complex or numerous properties, or behaviors that require more than just SVA. That is where helper code comes to the rescue. Helper code can significantly reduce the complexity of properties as well as be used to constrain formal analysis. Likewise, formal analysis may need to reduce the complexity of the problem and state space, which helper code can also help. So where are some places to use helper code and when?
This article looks at how helper code can be used to simplify our properties, model formal abstractions, constrain formal inputs, and aid formal analysis.
VIEW THIS ARTICLE ON THE DOULOS WEBSITE NOW »
Is formal verification ready for general use or do you need a PhD to use it? Larger companies continue to recruit formal PhDs into their verification teams while other less-well-qualified engineers seem reluctant to go beyond simplified formal "apps".
So, what is the truth of the matter? Can non-specialist engineers become productive with formal?
In this webinar Doulos Co-Founder and Technical Fellow, John Aynsley will explore the strengths and weaknesses of formal verification.
Using the VC Formal™ tool from Synopsys® as an example, John will explain exactly what you need to know to use formal effectively without acquiring deep knowledge of how it works under-the-hood.
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The aim is to provide you with a base to start learning the rest of UVM, starting at why you would want to use it and the key components of a UVM test bench. The webinar will provide an overview of the DUT interface and Sequencer-Driver communication.
The webinar will help you to understand:
- the class hierarchy
- simulation phases
- transaction-level communication
- sequences and sequencers
- drivers
- the factory
- the configuration database
- objections
The webinar will feature code examples running in QuestaSim from Siemens-EDA and aims to help you go on to learn the rest of UVM or to understand the rationale and working of automatically generated UVM code such as that produced by the Siemens-EDA UVM Framework code generator.
Doulos Senior Member Technical Staff, Matthew Taylor will present this training webinar.
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A common issue with constrained random simulation is being able to reproduce random stimulus for debug purposes and for locking down regressions test suites. This is especially problematic when the source code needs to be modified and is known in SystemVerilog as random stability.
In this webinar, we explain:
- Random stability in SystemVerilog and in UVM, the Universal Verification Methodology
- The pitfalls of poor random number generation and seeding
- How to ensure that simulation results are reproducible in native SystemVerilog and in UVM through a careful presentation of hierarchical seeding, manual seeding, thread stability, and object stability
- Exactly what changes you can and cannot make to UVM code without disturbing the random stimulus generation.
Examples written in the IEEE Std 1800™ SystemVerilog language and UVM 1.2 will be shown running on Cadence® Xcelium™.
This one-hour training webinar is presented by Doulos Senior Member Technical Staff, Matthew Taylor. Attendance is free of charge.
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View all on-demand webinars available »
About Doulos Training
For over 30 years, Doulos has been dedicated to developing the skills, capability and productivity of engineers designing the latest technologies.
The essential choice for independent training to over 5,400 companies spanning 84 countries, Doulos provides scheduled classes and bespoke team training both In-Person and Live Online. The course portfolio includes hardware design and verification languages and methodologies, embedded software, AI and deep learning.
Our business ethos is 'Service through Excellence' which, when combined with our industry-leading KnowHow™, makes Doulos the ideal training partner.
Contact Doulos now »
