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The Designer’s Guide to Verilog

The Verilog HDL is an IEEE standard hardware description language. It is widely used in the design of digital integrated circuits.

Here we provide some useful background information and a tutorial, which explains the basics of Verilog from a hardware designer's perspective. We also provide some useful tips and pointers to other Verilog information on the web site.

Upcoming Live Webinars

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A Guide to Productivity in Vivado using SystemVerilog

Wednesday February 18 2026

1 hour session (All Time Zones)

This webinar explores the features of SystemVerilog that are useful for RTL synthesis using the Vivado™ Design Suite from AMD, showing how the RTL SystemVerilog language constructs have been optimized for productivity and reliability.

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cocotb - An Introduction for Python Programmers

Friday February 20 2026

1 hour session (All Time Zones)

With many engineers having a working knowledge of Python, cocotb can prove a highly effective verification tool. This webinar will help you get started!

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What is an SBOM and why should I care?

Wednesday February 25 2026

1 hour session (All Time Zones)

In this webinar we are going to explain in as few words as possible what a Software Bill Of Materials (SBOM) is and why we need to know about them in embedded systems development.

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Anatomy of an Embedded Linux System

Friday March 06 2026

1 hour session (All Time Zones)

This introductory webinar will examine each of the components required for Linux to work on an embedded system. It will review how these components fit into the system and what functionality they provide for development and in the final deployed product.

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