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The Designer’s Guide to Verilog

The Verilog HDL is an IEEE standard hardware description language. It is widely used in the design of digital integrated circuits.

Here we provide some useful background information and a tutorial, which explains the basics of Verilog from a hardware designer's perspective. We also provide some useful tips and pointers to other Verilog information on the web site.

Upcoming Live Webinars

Zephyr Insights: Scheduling and Threads

Tuesday March 31 2026

1 hour session (All Time Zones)

This webinar delves into the services offered by Zephyr to ensure real-time behaviour, with a primary focus on threads, priority management, and scheduling, highlighting similarities and differences to other RTOSs.

Beginners' Guide to Using AI for Hardware Engineers

Friday April 10 2026

1 hour session (All Time Zones)

This webinar will examine how AI can help do a better job of engineering. Learn how to start integrating AI into your projects with real examples of AI used in hardware design and verification.

Getting Started with Embedded Linux Security

Wednesday April 15 2026

1 hour session (All Time Zones)

This webinar will examine some of the main features and tools which can be used to make your embedded Linux system more secure.

How can I use AI to improve my embedded C development?

Friday April 17 2026

1 hour session (All Time Zones)

This webinar explores the use of modern AI tools in practical embedded software engineering workflows to produce higher quality code more quickly.

Hypervisors in the Real World

Wednesday April 29 2026

1 hour session (All Time Zones)

This webinar explores how hypervisors provide robust workload isolation for mixed-criticality embedded applications.

Clock Domain Crossing

Wednesday May 06 2026

1 hour session (All Time Zones)

This webinar discusses situations in which CDC problems can occur and more importantly presents solutions for the most frequent scenarios.