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Designing Safe Finite State Machines

Wednesday September 24 2025

1 hour session (All Time Zones)
Presenter: Charles Gardiner

Doulos Certified Training Instructor
Presenter: Martin Kellermann
Marketing Business Development Manager, Microchip

Asia and Europe

Wednesday, September 24, 2025

Time: 10-11am (BST) 11am-12pm (CEST) 2.30-3.30pm (IST)

Register Now

Americas

Wednesday, September 24, 2025

Time: 10-11am (PDT) 11am-12pm (MDT) 12-1pm (CDT) 1-2pm (EDT)

Register Now

Webinar Overview:

Finite State Machines (FSMs) hold internal state information, react when inputs change, and then drive outputs. They are a foundational building block of FPGA or ASIC designs and have many names, including automatons, sequencers, controllers and Petri networks.

This webinar will introduce you to FSMs and elaborate on the practicalities of implementing and verifying them to meet reliability and safety requirements.

Topics include:

  1. Overview of FSM architectures
  2. FSM implementation & synthesis
  3. Causes of FSM failure
  4. Designing & verifying for safety
  5. Verifying safety on silicon

The webinar will also feature some real-world examples from Microchip Technology, using PolarFire® FPGAs and SoCs and the Libero® SoC Design Suite, demonstrating how the concepts work in a commercial FPGA device and tool chain.

Charles Gardiner

Charles Gardiner - Doulos Certified Training Instructor - will be presenting this training webinar, which will consist of a one-hour session and will be interactive with Q&A participation from attendees.

Martin Kellermann

Martin Kellermann - Marketing Business Development Manager of Microchip - will provide a practical real-world demonstration of how the concepts work.

Attendance is free of charge

If you have any queries, please contact webinars@doulos.com

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Visit www.doulos.com/knowhow/fpga/

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