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EDA Playground Live! VHDL Processes, Signals and Drivers

Tuesday March 17 2026

45 minute session (All Time Zones)
Presenter: Matthew Taylor

Doulos Senior Member Technical Staff

Asia and Europe

Tuesday, March 17, 2026

Time: 10-10.45am (GMT) 11-11.45am (CET) 3.30-4.15pm (IST)

Register Now

Americas

Tuesday, March 17, 2026

Time: 10-10.45am (PDT) 12-12.45pm (CDT) 1-1.45pm (EDT)

Register Now

Webinar Overview:

The VHDL language models hardware as a network of processes. Each process is a little bit of software that models a little bit of hardware. These processes communicate using signals. Having a good understanding of the mechanisms involved is vital to being able to write and understand VHDL code.

In this 45 minute webinar, Doulos Senior Member Technical Staff, Matthew Taylor, will explain these mechanisms through examples which are executed live on EDA Playground.


Topics covered are:

  •  Processes, Signal Assignments and Drivers
  •  Issues with multiple drivers, Longest Static Prefix
  •  Resolution Functions
  •  Implementing UVM-like Objections
  •  Driving Signals from Procedures
  •  Signal Attributes
  •  Passive Processes
  •  Force and Release

All attendees will receive access to the examples on EDA Playground using the Riviera-PRO™ Advanced Verification Platform from our webinar partner Aldec.

EDA Playground is an online simulation and synthesis environment provided by Doulos that is free to register and use. Find out more and start here: www.edaplayground.com

Matthew Taylor

Matthew Taylor Doulos Senior Member Technical Staff, will present this 30-minute webinar, which will include interactive attendee Q&A.

Attendance is free of charge

If you have any queries, please contact webinars@doulos.com

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