Thanks for taking the time to visit Doulos at this year's conference
This page has brought together a range of Doulos courses and FREE webinars and tutorials for you. Enjoy!
If you would like to explore training options with Doulos, check out the listing below and then contact your local Doulos team directly, or complete a webform*.
IP, FPGA and SoC Design and Verification Courses
Self-Paced Training
Upcoming EDA KnowHow Webinars
This webinar will examine how AI can help do a better job of engineering. Learn how to start integrating AI into your projects with real examples of AI used in hardware design and verification.
In this webinar Doulos Senior Member Technical Staff, Doug Smith, will cover:
- How AI works and the essential knowledge for picking the right AI models
- The practical application of Large Language Models (LLMs) in the EDA domain including the use of AI prompting, workflows, agents, and document stores
- Explore how these can be put to work in engineering projects
- An overview of how Siemens EDA are providing new AI-powered verification solutions in Questa One
If you are just getting started using AI, then join us to see how to practically put AI to work in your next project.
REGISTER NOW FOR THIS FREE KNOWHOW WEBINAR »
Today, most verification engineers’ language of choice is SystemVerilog, using UVM to create reusable verification components, environments and tests. Creating a reference model to verify RTL from scratch can be time-consuming and error-prone – so making use of algorithmic tools such as MATLAB® from MathWorks® can be very helpful.
In this webinar, we will look at how the SystemVerilog Direct Programming Interface can be used within UVM sequences and components. We will then go through the steps required to generate a reusable UVM checker from a simple MATLAB/Simulink® model, including:
- How to generate UVM code for a required coding style
- The use of parameters and the UVM configuration database
- Use of generated components within the UVM environment
- Running a simulation and checking the results
REGISTER NOW FOR THIS FREE KNOWHOW WEBINAR »
SystemC has become well-established as the language of choice for system modeling and virtual platform creation and integration, and is now being applied successfully for high level synthesis. SystemC models also frequently appear as reference models in the hardware verification flow.
This session is aimed at hands-on hardware or software engineers who might know Verilog or C but have no previous experience of SystemC. It will explain what you need to know to be successful with SystemC by exploring some fundamental questions including:
- What is SystemC and how is it used?
- What does modern SystemC code look like?
- What differentiates SystemC from SystemVerilog?
- What use cases best fit SystemC?
- What is TLM?
- Where can I learn more?
REGISTER NOW FOR THIS FREE KNOWHOW WEBINAR »
Check out the latest live webinar schedule »
EDA KnowHow Webinars On-Demand and Tutorials
Is formal verification ready for general use or do you need a PhD to use it? Larger companies continue to recruit formal PhDs into their verification teams while other less-well-qualified engineers seem reluctant to go beyond simplified formal "apps".
So, what is the truth of the matter? Can non-specialist engineers become productive with formal?
In this webinar Doulos Co-Founder and Technical Fellow, John Aynsley will explore the strengths and weaknesses of formal verification.
Using the VC Formal™ tool from Synopsys® as an example, John will explain exactly what you need to know to use formal effectively without acquiring deep knowledge of how it works under-the-hood.
REGISTER & VIEW THIS WEBINAR NOW »
Formal verification is known to work well in areas like control logic, interface protocols, and so on, but it is often dismissed for use on data paths since capacity becomes a significant issue. In particular, packet based protocols have potentially very large state spaces, which can pose a problem for formal. However, in this paper, a step by step process is presented, showing how to decompose a frame of data into simple formal constraints, modeling code, and assertions, which allows formal to fully explore the entire packet state space.
VIEW THIS TUTORIAL ON THE DOULOS WEBSITE NOW »
An advantage of using formal verification is how quickly a formal environment can be created with a few simple properties that immediately start finding design issues. However, not all design behaviors are easily modeled using SystemVerilog's property syntax, resulting in complex or numerous properties, or behaviors that require more than just SVA. That is where helper code comes to the rescue. Helper code can significantly reduce the complexity of properties as well as be used to constrain formal analysis. Likewise, formal analysis may need to reduce the complexity of the problem and state space, which helper code can also help. So where are some places to use helper code and when?
This article looks at how helper code can be used to simplify our properties, model formal abstractions, constrain formal inputs, and aid formal analysis.
VIEW THIS ARTICLE ON THE DOULOS WEBSITE NOW »
In this paper, eight common asynchronous scenarios are presented and SVA solutions for checking them. In addition, an alternative approach using a global fast clock is presented as both a portable simulation solution and something that works for both formal verification and emulation. Lastly, incorporating functional coverage into the asynchronous checking is also discussed.
VIEW THIS PAPER ON THE DOULOS WEBSITE NOW »
This webinar will explore the most common mistakes users of SystemVerilog make. These mistakes have been identified by observing the lab work of students participating in Doulos training classes. The webinar aims to help you avoid the pitfalls and, in the process, get your designs working faster.
Doulos CTI Brian Jensen, will explore the topics listed below and provide useful tips and resources to help you. Practical examples will be provided using QuestaSim from Siemens-EDA in the online simulation environment EDA Playground. The webinar will include live interactive Q&A participation for attendees with Doulos technical experts.
Topics include:
- Wire vs Variable Assignments
- Static vs Automatic Variables
- Static vs Automatic Tasks
- Assignments in Tasks – Pass-by-Copy
- Assignments in Tasks – Pass-by
- Reference
- Enumerations
- struct and packed struct
- Equality Operators
- Equality between vectors
- SVA Temporal Behavior
REGISTER & VIEW THIS WEBINAR NOW »
Learning any new programming language will undoubtedly be influenced by your existing design experience, and although that knowledge is largely very useful it can also work against you... For example, when you come to learn VHDL, the parallel nature of the hardware design language might trip you up if you've been using a language that has a sequential nature, such as Java, C or C++.
In this webinar VHDL guru, Doug Perry, (author of "VHDL: Programming by Example") explores some of the common mistakes designers make when starting out with VHDL and provides useful tips and resources for getting on track. Practical examples will be provided using Aldec Riviera-PRO™ in the online simulation environment EDA Playground.
Content Summary:
- VHDL Statements
- Process Statements
- Signal Assignments
- Delta Delays
- The Simulation Cycle
- Variables
- Incomplete Assignments
- Unexpected Latches
- Drivers
- Types
- Expressions
REGISTER & VIEW THIS WEBINAR NOW »
View all on-demand webinars available »
About Doulos Training
For over 30 years, Doulos has been dedicated to developing the skills, capability and productivity of engineers designing the latest technologies.
The essential choice for independent training to over 5,400 companies spanning 84 countries, Doulos provides scheduled classes and bespoke team training both In-Person and Live Online. The course portfolio includes hardware design and verification languages and methodologies, embedded software, AI and deep learning.
Our business ethos is 'Service through Excellence' which, when combined with our industry-leading KnowHow™, makes Doulos the ideal training partner.
Contact Doulos now »
