Beginner Level - Live Instructor-Led Training
2 days (In-Person) 8 hours per day or
4 sessions (Live Online) 4 hours per session
Essential Digital Design Techniques is a fast-track, application orientated course designed to bridge the gap between text book theory and real world digital design practice.
It significantly accelerates the on-the-job learning curve for engineers new to digital design, or those needing to refine their design skills before project involvement. With a strong emphasis on practical design and hands-on workshops, this course has been specifically developed to capture design techniques usually learned over months, in an intensive self-paced format.
Essential Digital Design Techniques provides the ideal first stage in full scale project training for graduate design engineers, or engineers moving into digital design from other disciplines (including software or analog design). As such, it is the natural precursor to other Doulos VHDL, Verilog and SystemVerilog courses, which prepare engineers for Hardware Design Language (HDL) application within FPGA or ASIC design projects.
Select the drop-down blocks below to find out more.
- New graduate engineers embarking on a first project, or engineers with limited practical experience of digital design.
- Engineers from other disciplines (e.g. physics, software design or analog electronic design) re-training for digital design involvement, or requiring familiarisation with modern digital design techniques.
Attendees require no prior involvement in digital design projects or HDL knowledge, but should be familiar with the basic principles of digital electronics.
- Combinational and Sequential Logic Design for FPGAs and ASICs, with an emphasis on synchronous design techniques
- How to design and implement fundamental structures e.g. decoders, multiplexers, shift registers, counters
- How to design and implement synchronous Finite State Machines
- An overview of ASIC and field programmable logic design including a survey of state of the art devices
- Designing with programmable devices
- Effective Design methodologies and flows
- Understand the role of on-chip buses with a focus on the de facto standard AMBA 3 APB/AXI bus protocols
PLEASE NOTE: this course does not teach, or require knowledge in a specific Hardware Description Language (HDL).
Doulos training materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique in the EDA training world, and has made them sought after resources in their own right. Fees include
- Fully indexed class notes creating a complete reference manual
- Workbook full of practical examples and solutions to help you apply your knowledge
- Access to course exercises and worked solutions on the free and open EDA Playground platform, which includes the use of a wide range of commercial and open source simulation and synthesis tools. Ongoing access to these course exercises remains available to attendees beyond the training, enabling ongoing learning through trials and experimentation.
Note: It is also possible, on request, to make course exercises available via AWS for team-based training. Please contact the Doulos team when enquiring.
Introduction
- Representing data using electronics
- Advantages of digital design over software and analog hardware
- Basic design flow and software tools
- Introducing Hardware Description Languages (HDLs)
Digital Design Basics
- Boolean algebra
- Combinational logic
- Implementing logic gates in hardware
- Asynchronous sequential logic
Synchronous Design
- Sequential logic, clocks and flip-flops
- Implementing sequential logic in hardware
- Timing violations
- Safe design rules
- Static timing analysis
- Types of flip-flop
Digital Design Technologies
- Application Specific Integrated Circuits (ASICs)
- Evolution of Programmable Logic Devices
- Volatile and non-volatile technologies
- Economic considerations
- Choosing between different technologies and devices
Design Practices
- Representing combinational logic in HDLs
- Representing sequential logic in HDLs
- Resource sharing
- Scalable design
- Design trade-offs
- Input hazards and metastability
- I/O buffers and I/O standards
- Three-state buses
- Pin locking
- Working safely with clocks and resets
Common Functions
- Encoders and decoders
- Priority encoders
- Multiplexers
- Parity generator
- Shift Registers
- Johnson (ring) "counters"
- Linear Feedback Shift Registers
Introduction to Buses
- Bus protocols and signal timing
- Transactions
- Bus architecture
- Addressing bus components
- AMBA APB
AMBA AXI Bus Protocol
- Advantages of AXI
- AXI 3/4
- Transactions
- Bus architecture
- Read, write and response channels
- Transaction ordering
- Burst transactions
- Further data handling options
- Component classes
Arithmetic Structures
- Unsigned and two's complement arithmetic
- Half and full adders
- Large adders
- Carry lookahead adder
- Pipelining
- Synthesis of adders
- Counters
- Serial arithmetic
Finite State Machines and IP Blocks
- Definition
- Graphical entry and symbolism
- Moore and Mealy structures
- Implementation
- State encoding and optimisation
- Using HDLs to design FSMs
- Using memories
- Memory types
- Using other complex functions
