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Xilinx - Vivado HLS ONLINE Jetzt Auf Deutsch

Auch bekannt als C-based Design: High-Level Synthesis with Vivado HLS by Xilinx. Früher AutoESL. Doulos Live Online training

Bitte beachten Sie: Hier handelt es sich um ein ONLINE-Training mit LIVE Dozent.

Es behandelt bei ähnlichem Lernerfolg den selben Inhalt wie ein klassisches Training.

Mehr über Doulos Online-Trainings hier »
Ich bin an einer Kombination von Xlininx-Trainings interessiert (kontaktieren Sie Doulos, um die Möglichkeiten zu erörtern) »

Scheduled Course Dates: German Language

Scheduled Course Dates: English Language

Course Dates:
September 30th, 2019	ONLINE EurAsia		Enquire
October 21st, 2019	ONLINE Americas		Enquire
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Upcoming Live Webinars

What Can Formal Do for Me?

Friday June 12 2026

1 hour session (All Time Zones)

This webinar will look at the ways formal helps your design verification process, including complexity analysis, bounded reachability analysis, overconstraining the design, setting cut points, and creating abstractions.

Introduction to Android Automotive

Wednesday June 17 2026

1 hour session (All Time Zones)

This webinar provides a valuable insight into the Android Automotive OS that runs "In Vehicle Infotainment" systems, from how it differs from mobile to writing 3rd party car apps.

Understanding MPSoC Real-Time Processing

Friday June 19 2026

1 hour session (All Time Zones)

Explore the Arm® powered real-time processing capability of the UltraScale+ MPSoC and the hardware and software requirements for implementing time sensitive applications.

AXI based Design & Verification

Wednesday June 24 2026

1 hour session (All Time Zones)

This webinar will cover the basics of on-chip buses, key terminologies and why we need them, before going deeper into AMBA : AXI bus architecture.

Creating UVM Components from MATLAB Models and SystemVerilog-DPI

Tuesday June 30 2026

1 hour session (All Time Zones)

This webinar will explore how the use of MATLAB Models and the SystemVerilog-DPI can help with the development and debugging of reference models for your design and verification projects.