Engineers with a need to verify FPGA/ASIC/Hardware IP designs, or who wish to rapidly upskill on efficient and effective verification techniques based on the cocotb Python framework, bypassing the need for ramping up on another hardware verification language (HVL) such as SystemVerilog and associated frameworks such as UVM.

• Hardware verification principles
• Key Python language features
• cocotb principles
• How to construct the different aspects of a verification environment using cocotb
• Verification strategies and tactics, including directed tests, boundary conditions, text-based test benches, constrained random verification, coverage measurement and creating reusable verification components
• Making use of 3^rd party packages for verification

Basic knowledge and experience of Python programming is desirable but not necessary as the course covers the Python language features that are needed.

A foundational knowledge of  digital hardware design (as covered by Doulos’ Essential Digital Design Techniques course) would be beneficial but not essential.

All labs will run on the online simulation environment from Doulos, EDA Playground, by default. EDA Playground contains all the leading commercial simulators, as well as a Python IDE, and is available to students to continue their learning post course completion.

Doulos training materials are renowned for being the most comprehensive and user friendly available. Their style, content and coverage is unique and has made them sought after resources in their own right. The materials include:

• Fully indexed class notes creating a complete reference manual
• A workbook full of practical examples and solutions to help you apply your knowledge.

Verification Basics
Verification Defined; What is the Verification Process; Introducing VHDL and SystemVerilog; Common Levels of Abstraction; Functional Verification; Approaches to Verification; Simulation; Simulating a Digital System; Design and Verification Tools; Simple Design and Verification Flow; Waveform Viewers; Basic Test Bench

Python and cocotb Basics
About Python; Characteristics of Python; The Python World; python.org; PyPI; About cocotb; Why use Python+cocotb for Verification?; Installing cocotb; cocotb Co-Simulation; cocotb Development; Supported IDEs and Simulators; The Python Shell; Strings and Comments; Functions; Dynamic Variables and Functions; Coroutines; Beginnings of a cocotb Test; Comparison and Boolean Operators; Checking Results; Waiting for Time to Pass; A Simple Complete cocotb Test; Running a Test; Test Summary

Exercise 1 – A Simple cocotb Test Bench

Values and Formatting
Numbers in Python; Strings in Python; Simple String Formatting; Type Conversions; VHDL Logic Values; SystemVerilog Logic Values; Boolean Values; Representing Positive Numbers; VHDL Logic Vectors; SystemVerilog Logic Vectors; Integers in Python; for Statements; Conditional Expression; Objects; HDL Element Objects; Reaching Inside the Design; Operators; Lines and Continuation; Reserved Words; Built-in Functions

Exercise 2 – Generating More Stimulus

cocotb Test Structure
Import; from... import; Packages; Top-level cocotb Test Structure; Test Decorator Parameters; cocotb Makefiles; Setting Makefile Variables; Mandatory Makefile Elements; TOPLEVEL v MODULE; A Few Useful Extra Makefile Options; A Simple cocotb Makefile; Case sensitivity; Logging Levels; Logging Thresholds; Logging Hierarchy; Redirecting Messages; Timing Stimulus and Checks; Structuring Tests Using Functions; Structuring Tests Using Coroutines; Other Build Mechanisms

Exercise 3 – A More Structured Test Bench

Creating a Verification Plan
Verification Planning; It all starts from the Specification; What needs to be verified?; Defining the Verification Plan; Don't Plan Everything

Flow Control and Synchronization
if Statements; match; break; continue; while statements; Function Arguments; Type Checking Function Arguments; Ways to Start Coroutines; Generating a Clock; Timing in a Synchronous Design; Waiting for the Clock; Clocks in Multiple Tests; ReadOnly Trigger; Example - 8-bit Counter in VHDL; Testing the Counter; Task-Specific Logging

Exercise 4 – Testing Sequential Logic

Strings and Lists
String Index; String Slice; Lists; List Operations; Splitting and Combining Strings; String Methods; Field Width, Justification, Padding; Number Base, Comma, Sign

Working with HDL Values
Logic in VHDL and SystemVerilog; cocotb Logic Types; Signed Numbers; Converting Between Positive and Negative; Two's Complement Examples; Sign Extension; Signed and Unsigned in HDL; Range; LogicArray; LogicArray Examples; Manipulating LogicArray Directly; Assigning LogicArray Elements and Slices; LogicArray .range Attribute; LogicArray Unsigned Integer Conversions; LogicArray Signed Integer Conversions; LogicArray String Type Conversions; Comparing LogicArray Representations

Exercise 5 – Handling Different Kinds of Values

Files and Exceptions
Test Benches and Text Files; Writing to a File; Reading from a File; What is an Exception?; Handling Exceptions; More on Exceptions; Context Manager; The os Module; os.environ; os.path; pathlib; Running OS Programs; Configuring Your Test Bench

Exercise 6 – Text Files

Further Verification Packages
Bottom Up and Top Down; Verification Methods; Tactics: Analysis to Define Tests; Tactics: Boundaries and Corners; Tactics: Regression Testing; Tactics: Stress Testing; Different Sorts of Stimulus; Testcases; Improving Simulation Speed

Collections of Values
More List Operations; Loops and Lists; Sorting Lists; Removing and Deleting; List Comparison; Tuple = Immutable List; Sequence versus Iterator; Iterables and Iterators; List Comprehensions; Dictionaries; Dictionary Operations; Keys and Values; More Dictionary Operations; Verification Example - Lists; Verification Example - Dictionaries; Accessing HDL Lists

Exercise 7 – Verification Tactics

Classes and Objects
Classes; Multiple Objects; Attributes and Method Arguments; Constructors; Class Variables and Instance Variables; Ways of Calling Methods; Variables and Objects; Documentation Strings; Type Hints; Inheritance; Overriding Methods; Virtual Method Calls; Class Relationships; Copying Instance Objects; Test Bench as a Class

Exercise 8 – A Class-Based Test Bench

Transaction Level Verification
Basic Test Bench; Monolithic Test Benches are Inflexible; Bus Functional Modeling; Hiding the DUT Interface; Example Driver Class; Setting Constants; Transaction Level Test Bench

Exercise 9 – An APB Driver

Transactions and Randomization
Transaction Class; Magic Methods; Comparison Magic Method; Some Useful Magic Methods; Verification Methodology; How Do We Generate Better Stimulus?; random; Randomizing a Transaction; Random Well-Defined Transactions; Weight Constraints; Excluding Values; More Complex Constraints; Adding Constraints to a Transaction; Predictable Random Stimulus

Exercise 10 – Transactions and Randomization

Reusable Verification Components
Test Bench Design Principles; Example Verification Environment; Different Kinds of Component; Communicating Transactions; cocotb Queue as a Channel; Example Stimulus Generator Class; Example Driver Class; Fetching and Driving Transactions; Monitor BFM; Example Monitor Class; Initial Top-Level Test Bench Class; Faster Component Development; Random Stability

Exercise 11 – Verification Components

Checking and Coverage
Monitors and Checkers; What are we Checking?; Finishing the Simulation; Example Checker for a Single Interface; Checking Mechanisms; Completing the Verification Methodology; Functional Coverage; Coverpoints; Coverage Bins; A Generic Coverage Class; Coverage Collector Component; Coverage Collector Base Class; Reporting Coverage; Example Transaction Coverage Class; Configuring Coverage and Randomization; Completing the Top-level Test Bench

Exercise 12 – Checking and Coverage

Matrix Data with NumPy
Using Python for High Level Data; A 1D NumPy Array; A 2D Array or Matrix; Initializing Arrays; Arithmetic Series; Copying the Shape of an Existing Array; Random Arrays; Elementwise Operations; Combining Arrays and Scalars; Broadcasting; Broadcasting in Two Dimensions; Vectorizing a Function; Array-of-Indices; Indexing with Array-of-Booleans; Other Operations

High-Level Data Manipulation
Introduction to Pandas; Pandas Data Structures; Pandas Series; Pandas Data Frames; SQL-Like Operations in Pandas; Basic Statistics in Pandas; Pandas Data Transformations; Introduction to Matplotlib; Matplotlib Subplots; Plotting with Lines, Colors and Markers; Types of Plot in Matplotlib; Plotting a Histogram in Matplotlib; Plotting an Array as a Grid in Matplotlib; Other Python Packages

Exercise 13 – Using Additional Python Packages

Structured Verification Methodologies
Standard Verification Methodologies; Verification IP; pyuvm; Introduction to Forastero; Forastero Port Naming Convention; Forastero Examples; Constraint Solvers; lambda; Introduction to constrainedrandom; constrainedrandom Example; constrainedrandom domains; Introduction to PyVSC; PyVSC Random Stimulus Example; PyVSC Covergroup Example; Other Coverage Packages; Apheleia Verification Library