Introduction
What is SystemVerilog? • History • Language Evolution • Language Features in SystemVerilog • Design Flow • Tools • SRAM-based FPGAs • SRAM FPGAs - Typical Logic Block • FPGAs - Extra Features • Typical Functional Simulation Flow • Typical Synthesis Flow • Recommended Design Style for Synthesis • Timing Constraints • Typical FPGA Implementation Flow • Timing Simulation & Download • Benefits of SystemVerilog • SystemVerilog Books • Verilog Resources • SystemVerilog Resources
Modules
Modules and Ports • Continuous Assignment • Rules and Regulations • Single-line vs Block Comments • Names • Reserved Identifiers • Internal connections • `default_nettype • Hierarchy • Port Connection Shorthand • Unconnected Ports • Test Fixtures • Outline of Test Fixture for MUX2 • Initial Blocks • Variables • $monitor • The Complete Test Fixture • Introduction to Tcl Scripts • A Tcl Example
Numbers and Formatting
Logic Values • 4-state Integer Types • 2-state Integer Types • 2-State and 4-State Values • Vectors • Numbers • Truncation and Extension • Signed Numbers • "Disguised" Binary Numbers • More than 32 bits • Formatted Output • Formatting • Formatting Text • Timeunit and Timeprecision • Formatting Time Values • $timeformat • Always • $stop and $finish • Default time units
Always Blocks
RTL Always Statements • Sensitivity List for Combinational Logic • always_comb • If Statements • Begin-End • Else If • Nested If and Begin-End • Incomplete Assignment • FPGAs and Transparent Latches • Unknown and Don't Care • Conditional Operator • Unknowns in Conditionals • Parallel Procedural Assignments • Parallel Continuous Assignments • Tristates
Procedural Statements
Case Statement • Case Statement Continued • Casez Pattern Matching • Casex Pattern Matching • Casez and Casex Truth Tables • Priority Encoder Using Case • Full and Parallel Case Statements • Careless Casez • Unique and Priority Case • One-Hot Decoder Using Case • Unique If • Loop Statements • SystemVerilog for loop • For Loop Syntheis • For Loop Variable Declaration • do...while, break, and continue • Loops in Test Fixtures • Local Variables • Labelling (1) • Labelling (2) • Disable • Combinational Always
Clocks and Flip-flops
Edge Triggered Flip-Flop • Avoiding Simulation Races • The SystemVerilog Scheduler • Blocking, Non-blocking, and #0 • Nonblocking Assignments • Asynchronous Set or Reset • Synchronous and Asymchronous Actions • Clock Enables • iff • Synthesis Templates • RTL Synthesis Tool Architecture • RTL Synthesis • Creating Flip-Flops • Flip-Flop Inference - Blocking Assignment • Flip-Flop Inference - Nonblocking • Flip-Flops Quiz 1 • Flip-Flops Quiz 1 - Answer • Flip-Flops Quiz 2 • Flip-Flops Quiz 2 - Answer • Flip-Flop Merging • No Flip-Flop Optimization • Optimized By Hand
Operators and Names
Bitwise and Reduction Operators • Logical Operators • Equality Operators • Equality between Vectors • Part Selects • Indexed Part Select • Concatenation • Shift Registers • Shift Operators • Replication • Summary of Operators • Beware++ • Hierarchical Names • Upwards Name References
Memories
Packed and Unpacked Arrays • Indexing Array Elements • Array Layout • Array Operations • Array Copying • Packed Arrays as Integers • Array Querying Functions (1) • Array Querying Functions (2) • $bits • Packed Arrays and Concatenation • Braces in SystemVerilog • Unpacked Array Initialization • Default • Memories and Synthesis • Memories • RAMs • Instantiating Memories • Loading Memories
FSM Synthesis
Finite State Machines • State Transition Diagrams • Enumerations • Type-Checking of Enumerations • Overriding the Default Values and Type • Default Value of an Enum Variable • Various Rules for Enumerations • Explicit State Machine Description • State Machine Architecture • Timing in a Synchronous Design • Separate Output Decoding • Separating Registers from C-logic(1) • Separating Registers from C-logic(2) • No Output Decoding • One-Hot Using Case • State Encoding • Unreachable States • Controlling Unreachable States
Types and Packages
4-state and 2-state Types • Initial Values • Examples • Caveats with Signed Types • Enumerations, Arrays, typedef • struct • typedef struct • Packed Struct • Packed Struct - Another Example • Packed Union • Multidimensional Arrays • Odds and Ends • Nets, Ports and Data Types • Concurrent Assignment to a Net • Variables and Data Types • Concurrent Assignment to a Variable • Packages • Packages and Ports • Packages - Another Example
Arithmetic
Synthesis of Arithmetic Operators • Vector Arithmetic • Signed Types • Behaviour of Signed Types (1) • Behaviour of Signed Types (2) • Unsigned versus Signed • Arithmetic Expressions • Arithmetic Examples (1) • Arithmetic Examples (2) • Integer and Syntheis • Arithmetic Operators • Choice of Adders • Arithmetic Isn't Optimized • Arithmetic Really Isn't Optimized • Arithmetic WYSIWYG • Resource Sharing • Manual Resource Sharing
File Organisation and Parameters
Compliation • Compliation Units • Declarations Outside Modules • Compile Options • SystemVerilog Preprocessor • `define and `include • `ifdef • Enhanced Conditional Compilation • Parameters • Overriding Parameters • localparam • Using Parameters • generate • generate for • generate if • generate - case SystemVerilog • generate - Tool Support
Interfaces
Introduction to Interfaces • APB with Master and Single Slave • Why Not Use a Struct? • Interface • Using an Interface (1) • Using an Interface (2) • Accessing Interface Members • Modports • Modport Declarations • Connecting Ports Using Modports • Interface Ports and Parameters • Synthesis Example • Synthesis Results • Imported Functions for Design • Implementation • Multiple Drivers on a Bus • Bus Readback Challenges • Modport Expressions • Modport Expressions and Generate • Generate the Attached Modules • Applications for Interfaces (1) • Applications for Interfaces (2) • Applications for Interfaces (3)
Tasks and Functions
Tasks • Calling (Enabling) a Task • Task Arguments • Task Argument Passing • Static versus Automatic Storage • Other Task Features • ref arguments • Functions • Task vs. Void Function • Synthesisable Functions • Synthesis of Tasks • Calling RTL Tasks
File I/O
Modelling the Test Environment • System Tasks for Output • $strobe • Writing to Files • Opening and Closing Files • File Modes • Reading From a File - Formatted Data • Formatting the Data for $fscanf • $fscanf • $fscanf - Summary • Strings • String Operations • String Methods • $ • $sformat and $sformatf • Reading a File Line by Line • Diagnosing File I/O Errors • Immediate Assertions • File I/O - Summary
Gate Level Simulation & C Interfacing
Basic Design Flow • Why Simulate the Gates? • Verilog Flow for PLD Design • Design Flow for ASIC Design • "Classic" Verilog Libraries • Comparison On-the-fly • Direct Programming Interface (DPI) • DPI Simulation Flow • Importing C Functions • C Function Name and Arguments • Exporting Functions to C • DPI: Mapping Data Types • Scalar Bit and Logic Values • Packed Arrays • Other Types • Arguments and Return Values
Appendix - Clocking Blocks
Clocking Blocks • Clocking Block Syntax • Input and Output Skew • Creating a Clocking Block • Testbench and Clocking Block • Cycle Delays and Clocking • Input and Output Skew Syntax Summary • Scheduler Regions • Clocking Blocks versus Programs
Appendix - The SVA Language
What are SystemVerilog Assertions? • Property versus Assertion • What are Properties? • Why Use Assertions? • Who Writes Properties and Assertions? • Immediate and Concurrent Assertions • Immediate Assertions • Concurrent assertions • Temporal Behaviour • Clocks and Default Clocks • Holds and Implication • Non-overlapped Implication • Simulation of Assertions • Assertion Coverage • Simulation and Cover Property • Example • Implication • Properties are checked on every clock • Properties using Expressions • $rose() and $fell() • Using $past() • $past() • Support for Assertions • Assertion Sampling • Named Properties • Sequences • Concatenation and Repetition • Non-Consecutive and Goto Repetition • Sequence versus Implication • Quiz 1 • Quiz 1 (Solution) • Binding • Binding Example
