Verification Basics
Verification Defined • Some Related Definitions • What is the Verification Process? • Common Levels of Abstraction • Functional Verification • Approaches to Verification • Simulation • Simulating a Digital System • Waveform Viewers • Basic Test Bench
Python and cocotb Basics
About Python • The Python World • Characteristics of Python • About cocotb • cocotb Co-Simulation • The Python Shell • Comments • Functions • Coroutines • Beginnings of a cocotb Test • Referencing Device Ports • Comparison and Boolean Operators • Checking Results • Waiting for Time to Pass • A Simple cocotb Test • Running a Test • Test Summary
Lab: Making minor modifications to a pre-existing test, and running it
Values and Formatting
Numbers in Python • Strings in Python • Simple String Formatting • Type Conversions • VHDL Logic Values • SystemVerilog Logic Values • Representing Positive Numbers • VHDL Logic Vectors • SystemVerilog Logic Vectors • Integers in Python • for Statements • Objects • HDL Element Objects • Reaching Inside the Design • Operators • Lines and Continuation • Built-in Functions
Lab: Adding further tests for the DUT used in ex01, including improving the way the stimulus is generated and checked by using a for loop
cocotb Test Structure
import • from… import • Packages • Top-level cocotb Test Structure • cocotb Makefiles • Setting Makefile Variables • Mandatory Makefile Elements • TOPLEVEL v MODULE • A Few Useful Extra Makefile Options • A Sample cocotb Makefile • Case Sensitivity • Logging • Logging Levels • Logging Thresholds • Logging Hierarchy • Timing Stimulus and Checks • Structuring Tests Using Functions • Structuring Tests Using Coroutines
Lab: Writing a testbench and makefile for a “Min-Max” circuit. This should be structured using functions and include some log messages
Creating a Verification Plan
Verification Plan • Verification Planning • It all starts from the Specification • What Needs to be Verified • Defining the Verification Plan • Don't Plan Everything
Flow Control and Synchronization
if Statements • break • continue • while Statements • Ways to Start Coroutines • Generating a Clock • Timing in a Synchronous Design • Waiting for the Clock • Example - 8-bit Counter in VHDL • Testing the Counter • Task-Specific Logging
Lab: Writing a testbench and makefile for a counter
Strings and Lists
String Index • String Slice • Lists • List Operations • Splitting and Combining Strings • String Methods • Field Width, Justification, Padding • Number Base, Comma, Sign
Working with HDL values
Logic in VHDL and SystemVerilog • cocotb Logic Type • Signed Numbers • Converting between positive and negative • Two's Complement Examples • Sign Extension • Signed and unsigned in HDL • integer and signed_integer • binstr • LogicArray • Range • LogicArray .range Attribute • More LogicArray Examples • Manipulating LogicArray • Comparing Different Logic Representations
Lab: Writing a testbench and makefile for an ALU (self-checking and handle negative values)
Files and Exceptions
Testbenches and Text Files • Writing to a File • Reading from a File • Handling Exceptions • More On Exceptions • Context Manager • The os Module • os.environ • os.path • Running OS Programs
Lab: writing a test bench to read commands from a text file and apply them to the device under test (test runner).
Further Verification Principles
Bottom up v Top down • Verification Methods • Tactics: Analysis to Define Tests • Tactics: More Analysis to Define Tests • Tactics: Boundaries and Corners • Tactics: Regression Testing • Tactics: Stress Testing • Different Sorts of Stimulus • Testcases
Collections of Values
More List Operations • Loops and Lists • Sorting Lists • Removing and Deleting • List Comparison • Tuple = Immutable List • Sequence versus Iterator • Iterables and Iterators • List Comprehensions • Dictionaries • Dictionary Operations • More Dictionary Operations • Dictionary Comprehension • Verification Example - Lists • Verification Example - Dictionaries • Accessing HDL Arrays
Lab: Writing a testbench and makefile for a BCD counter, including boundary conditions such as the point at which the count values wrap.
Classes and Objects
Classes • Classes and Methods • Constructors • Class Variables and Instance Variables • Class vs Object vs Function vs Method • Variables and Objects • Documentation Strings • Inheritance • Overriding Methods • Another Example • Virtual Method Calls • Copying Instance Objects • Copying Lists • Assigning Lists • Assigning to a Slice • Shallow Copying • Test Bench as a Class
Lab: Writing a class-structured, text-based testbench and runner to test the FSM
Transaction Level Verification
Basic Test Bench • Monolithic Test Benches are Inflexible • Bus Functional Modeling • Hiding the DUT Interface • Example Driver BFM Class • Setting Constants • Transaction Level Test Bench
Lab: Writing an APB BFM to test a dummy APB Memory
Reusable Verification Components
Transaction Level Modeling • Components as objects • Transactions as objects • Stimulus Generator • Queue • cocotb-bus Driver • Constrained Random Tests • The Python random module • Generating random stimulus • Random sequence of well-defined actions • Predictable stimulus (RANDOM_SEED) • Constraining Stimulus using weights
Lab: Completing a class-based verification environment for the APB_mem
Checking and Coverage
Monitors and Checkers • What are we checking? • Finishing the Simulation •Checking Mechanisms • Completing the verification Methodology • Functional Coverage • Coverpoints • Coverage Bins • A Generic Coverpoint Class • Coverage Collector Component • Coverage Collector Base Class • Reporting Coverage • Configuring Coverage Randomization • Coverage Improvements •Completing the Top-level Test Bench
Lab: add a checker and coverage collector to a class-based test bench with already contains a stimulus generator, a driver and monitor.
Structured Verification Methodologies
Standard Verification Methodologies •pyuvm •Introduction to Forastero • Forastero Port Naming Convention • Forestero Interface Class Example • Introduction to PyVSC •PyUVC Random Stimulus Example • PyVSC Covergroup Example • cocotbext-axi
Matrix Data with NumPy
Using Python for High Level Data • A 1D NumPy Array • A 2D Array or Matrix • Initializing Arrays • Arithmetic Series • Random Arrays • Row and Column Vectors • transpose • Sorting • Reduction Functions • Elementwise Operations • Combining Arrays and Scalars • Broadcasting • Broadcasting in Two Dimensions • Dot Product • Vectorizing a Function • Array-of-Indices • Indexing with Array-of-Booleans • Concatenate and Stack • Split
High-Level Data Manipulation
Introduction to Pandas • Pandas Data Structures • Pandas Series • Pandas DataFrames •SQL-Like Operations in Panadas • Basic Statistics in Panadas • Pandas Data Transformations • Introduction to Matplatlib • Matpltlib Subplots • Other Python Packages
Lab: write a test bench which uses NumPy and Matplotlib to help verify the output from a behavioral sine wave generator
