This webinar explores common mistakes and solutions to memory usage in C and C++ using the heap.

The webinar includes:

• Approaches to avoiding memory usage bugs by illustration
• Contrasts between the C and C++ programming languages

The presentation applies to general purpose programming, small embedded systems (bare-metal and RTOS) and large embedded (Linux) systems. A minimal knowledge of C and/or C++ is required to attend.

The webinar is run in partnership with IAR, who will provide a brief working example of using their C-RUN software to provide memory safe checking for C & C++ code.

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As the necessity for robust cybersecurity is being shaped by international compliance legislation, device makers face new obligations across their product lifecycle, from development to EOL.

Using the EU Cyber Resilience Act (CRA) as an example, this joint webinar from Toradex, NXP & Doulos will demonstrate that getting your cybersecurity risk assessment and threat modeling right isn’t just a box to tick - it's actually the foundation of all of your compliance activities. 

This webinar will provide: 

• A view of the CRA’s stipulation for a risk assessment and the evolving standards landscape, to see what will likely be strictly required.
• A look at the effect a product’s risk assessment has on the rest of its CRA compliance obligations, to illustrate why it’s so important.
• A practical introduction to threat modeling, with real-world examples.
• An overview to how hardware security features can provide concrete security controls that can shrink attack surfaces and make threat models easier to manage.
• An example of a successful implementation of the risk analysis process. 
  
  

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This webinar will explore ideas on identifying and deploying trained AI models on FPGAs. Doulos Member Technical Staff, Dr Rahul Dubey, will discuss contemporary software tools and APIs which help in putting together an FPGA based Edge AI solution.

We will be using the AMD PYNQ™ Python based Hardware/Software stack on FPGA based System-on-Module platforms as an illustration.

Webinar topics include:

• Overview of Edge Inference options
• Application requirements for model selection
• Using a model from a model zoo
• Use of AMD Vitis™ AI to prepare a custom AI model for a Kria™ SoM
• Prototyping considerations using the Kria Starter Kit
• Using the AMD PYNQ Base Overlay, Deep Learning Processor Unit and Composable Pipeline.
  
  

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Formal proofs of end-to-end properties can be a very valuable contribution to RTL sign-off and yet are often the most difficult to achieve.

In this webinar Doulos Senior Member Technical Staff, Doug Smith will explore some practical ways of dealing with inconclusive formal proofs when using the Jasper Formal Verification Platform by Cadence. This includes the use of complexity analysis and bounded reachability analysis, over-constraining the design, setting cut points, and creating abstractions.

This webinar will be useful to anyone who wants to learn to make more effective use of formal.

Webinar topics include:

• Formal Verification Overview
• Formal Apps
• Formal Coverage
• Assertion Coverage
• Inconclusive Formal Proofs
• Cut Points and Abstraction

Attendance is FREE and live Q&A will be provided throughout the broadcast.

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The Portable Test and Stimulus Standard (PSS) from Accellera is an evolution in Constrained Random Verification. With ordinary Constrained Random Verification, some things (like input data for example) are certainly random, but ultimately you have to write the tests yourself.

PSS is a new language that allows you to specify verification intent and use tools, such as Siemens Questa™ One Sim software, to create random tests for you. These tests can be realized to run across various platforms, tools, and verification stages. So, for example, a randomly generated test could be used to start sequences on a UVM testbench, or realized as software running on an embedded CPU.

In this webinar Doulos Senior Member Technical Staff, Matthew Taylor will:

• Illustrate what PSS can do for you using a simple UVM example
• Provide details about the PSS language itself
• Explain the differences between PSS and other languages
• Provide some examples using Siemens Questa One Sim
  
  

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Dr David Long, Doulos Principal Member Technical Staff, looks at how to get started on a "small embedded" system built around a microcontroller and firmware running "Bare Metal" or with a Real Time Operating System (RTOS). 

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This webinar will examine the application of AI in Edge / IoT situations. Although it uses an example for an industrial application, it will be of interest to anyone considering the use of AI technology for constrained devices.

The webinar includes:

• recommendations on quality data acquisition
• how to use metrics to test model performance
• the use of transfer learning to create custom models
• AI model quantization and API's for model inference

Two hypothetical edge AI based factory application examples are used, as well as a brief explanation of how Edge AI is deployed to remotely located edge devices, such as the RZ Family of MPUs from Renesas.

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This is the first in a series of webinars to help you gather the essential KnowHow you need to start using Zephyr.

To begin, we will provide a brief background on the open-source Zephyr project and real-time systems. Next, we will delve into the services offered by Zephyr to ensure real-time behaviour, with a primary focus on threads, priority management, and scheduling. Throughout this webinar, we will highlight similarities and differences compared to other Real-Time Operating Systems.

To make these concepts more tangible, we will run code samples on a development board with Percepio Tracealyzer and a brief look at IAR's Arm toolchain.

By the end of this session, attendees will have gained a solid understanding of how Zephyr can be employed for creating real-time systems.

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Although not originally designed for embedded software development, the C language allows a range of programming styles from high-level application code down to direct low-level manipulation of hardware registers. As a result, C has become the most popular programming language for embedded systems today.

This webinar is intended for anyone who is new to embedded systems or who wishes to start using the C language for an embedded application. The presentation is produced and delivered by Doulos, with thanks to Siemens for providing part of the content.  

You can expect to learn about:

• Alternative approaches and languages used for embedded software development.
• The features that make C the first choice programming language for both large and small embedded systems.
• Details about key C language constructs used to write code for essential embedded system tasks such as:
  • accessing data in memory and registers;
  • working with interrupts;
  • driving peripheral devices.
    
    

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A memory scribble or some other access violation in user space is likely to cause an undefined instruction or a data abort exception which will trigger a "SIGSEGV" segmentation fault, e.g.:

target$ ./my_app
Segmentation fault
target$

The basic information provided does not provide any clues as to what the problem is. In this article we take a brief look at some of the tools there available in a typical embedded Linux development environment which can help to track down the problem.

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Working with embedded Linux, Yocto and Git inevitably means spending a lot of time working on the command line, on your host as well as on the target embedded system. There are plenty of useful shortcuts and tricks we can use to make this job a lot easier.

This "Linux, Yocto & Git commands booklet", created by the Doulos Embedded technical team, provides a handy reminder of how to work on the command line, with examples of how to work with files and folders, searching, managing archives and much more. It also includes some useful tips for working with VI, the standard Linux text editor.

Click here to download this commands sheet in PDF format. 

This webinar will explore the most common mistakes users of SystemVerilog make. These mistakes have been identified by observing the lab work of students participating in Doulos training classes. The webinar aims to help you avoid the pitfalls and, in the process, get your designs working faster.

Doulos CTI Brian Jensen, will explore the topics listed below and provide useful tips and resources to help you. Practical examples will be provided using QuestaSim from Siemens-EDA in the online simulation environment EDA Playground. The webinar will include live interactive Q&A participation for attendees with Doulos technical experts.

Topics include:

• Wire vs Variable Assignments
• Static vs Automatic Variables
• Static vs Automatic Tasks
• Assignments in Tasks – Pass-by-Copy
• Assignments in Tasks – Pass-by
• Reference
• Enumerations
• struct and packed struct
• Equality Operators
• Equality between vectors
• SVA Temporal Behavior

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This webinar will introduce you to the Universal Verification Methodology.

The aim is to provide you with a base to start learning the rest of UVM, starting at why you would want to use it and the key components of a UVM test bench. The webinar will provide an overview of the DUT interface and Sequencer-Driver communication.

The webinar will help you to understand:

• the class hierarchy
• simulation phases
• transaction-level communication
• sequences and sequencers
• drivers
• the factory
• the configuration database
• objections

This webinar is run in partnership with Siemens EDA and will feature code examples running in the Questa Advanced Simulator. The aim is to help you go on to learn the rest of UVM or to understand the rationale and working of automatically generated UVM code such as that produced by the Siemens EDA UVM Framework and Doulos' Easier UVM code generators.

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